I am a POSTECH postdoctoral researcher focused on compact wireline and optical
transceiver architectures for short-reach, chip-to-chip, and co-packaged optics
applications.
My doctoral and postdoctoral work bridges circuit design and system-level
signal integrity. I specialize in high-speed wireline communication and energy-efficient TRX design.
With 5 journal and 4 conference papers (including ISSCC 2022) plus a
U.S. patent [P1], I deliver silicon-proven architectures.
Ph.D. in Electrical Engineering, POSTECH, Korea (2019–2025) • GPA 3.95/4.3 • Advisor: Prof. Byungsub Kim
Dissertation: "Design of Compact and Energy-Efficient Inverter-based High-Speed Transmitter"[PDF]
B.S. in Electrical Engineering, POSTECH, Korea (2014–2018) • GPA 3.63/4.3
The prototype was implemented in a 28-nm CMOS process.
Key concepts: (1) A-FFE completely eliminates subtractions between FFE taps. (2) A-FFE allows the use of inverter drivers as FFE taps. (3) A-FFE saves unnecessary power consumption by tap subtractions. (4) A-FFE is robust to quantization errors of tap coefficients because the error signals are suppressed by the channel loss.
Achieved a data rate of 20 Gb/s and the worst eye sensitivity of 68% with a 15-dB PCB trace, while consuming 1.18 pJ/b.
The eye opening decreased by only 13.6%, when the most sensitive FFE coefficient was reduced by 20%.
Presented in IEEE International Solid-State Circuits Conference (ISSCC) 2022 [C1] and published in IEEE Journal of Solid-State Circuits (JSSC) 2024 [J3].
Registered with a U.S. patent [P1] and awarded in Korea Semiconductor Design Contest (Corporate Special Awards) [A1].
Single-Ended PAM4 TXs With Crosstalk Compensation (XTC) for Short-Reach Interfaces
[Lead Designer – 1st Author]
The prototype was implemented in a 28-nm CMOS process.
Key concepts: (1) Simple encoders and transition detectors detect the PAM4 data patterns causing crosstalk and activate inverter-based XTC taps. (2) With gain and delay control of XTC, compensation error due to the mismatch was minimized.
Achieved a data rate of 16 Gb/s with an energy efficiency of 1.6 pJ/bit.
With XTC, the eye height and width were improved by 203% and 396%, respectively.
Published in IEEE Transactions on Circuits and System II: Express Briefs (TCAS II) 2024 [J2].
Single-Ended Data-Embedded Clock Signaling (DECS) for On-Chip Links
[Co-Designer]
The prototype was implemented in a 28-nm CMOS process.
Key concepts: (1) RX recovers and deserializes the data from the DECS input without CDR/CDA. (2) Using the same clock source for both DECS and forwarding clock improves timing margins and tolerance to duty cycle error and supply noise.
Achieved a data rate of 20 Gb/s/pin with an energy efficiency of 1.27 pJ/b and a wide eye width of 0.99 UI at BER of 10-10.
Achieved an eye width of 0.88 UI for the clock duty cycle between 40% and 60%, and an eye width of 0.88 UI with the 50-MHz 300-mVpp RX supply noise.
Presented in IEEE International Solid-State Circuits Conference (ISSCC) 2022 [C2] and published in IEEE Journal of Solid-State Circuits (JSSC) 2023 [J4].
High-Speed Optical Link
100 Gb/s Microring Modulator Driver (Ongoing)
[Lead Designer]
The prototype is being implemented in a 28-nm CMOS process.
Key concepts: (1) The output driver uses a differential ac-coupled architecture to maximize output voltage and decouple it from MRM bias by utilizing an on-chip bias-T. (2) The output driver consists of a pseudo-differential stacked push-pull output stage to deliver 2.35 Vppd output swing while satisfying the electrical overstress requirements. (3) Inverter-based Cherry-Hooper amplifiers are used in the pre-driver to enhance the bandwidth.
Achieved a data rate of 100 Gb/s with an energy efficiency of 1.45 pJ/bit in simulation.
Publications
From JSSC to ISSCC Spotlight Sessions
Journal Papers (5 papers, 3 first-author)
[J1] OJ-SSCS 2024: C. Moon, M. Choi, M. Lee, and B. Kim, "Review on Resistive Termination
Techniques Driven by Wireline Channel Behaviors," vol. 4, pp. 305-317, Dec. 2024.
LINK
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[J2] TCAS-II 2024: C. Moon, I. Jang, S. Lim, Y. Huh, and B. Kim, "3 × 16 Gb/s Compact Single-ended
PAM4 Transmitters with Inverter-based Crosstalk Compensation for Memory Interfaces," vol. 71, no. 12, pp. 4884-4888, Dec. 2024.
LINK
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[J3] JSSC 2024: C. Moon, J. Seo, M. Lee, I. Jang, and B. Kim, "A Single-Ended Inverter-based
Addition-Only Feed-Forward Equalization Transmitter," vol. 59, no. 11, pp. 3741-3751, Nov. 2024.
LINK
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[J4] TCAS-I 2024: M. Lee, J. Cho, J. Choi, W. J. Choi, J. Lee, I. Jang, C. Moon, G. Kim, and B. Kim,
"Compact Single-ended Transceivers Demonstrating Flexible Generation of 1/N-rate Receiver Front-ends for Short-Reach Links,"
vol. 71, no. 1, pp. 373-382, Jan. 2024.
LINK
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[J5] JSSC 2023: J. Seo, S. Lee, M. Lee, C. Moon, and B. Kim, "A 20-Gb/s/pin Compact Single-Ended
DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links," vol. 58, no. 11, pp. 3253-3265, Nov. 2023.
LINK
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Conference Papers (4 papers, 1 first-author at ISSCC)
[C1] ISSCC 2022: C. Moon, J. Seo, M. Lee, I. Jang, and B. Kim, "A 20 Gb/s/pin 1.18 pJ/b
1149μm² Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness
to Coefficient Errors in 28nm CMOS," pp. 450-451, Feb. 2022.
LINK
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[C2] ISSCC 2022: J. Seo, S. Lee, M. Lee, C. Moon, and B. Kim, "A 20-Gb/s/pin 0.0024-mm²
Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error
and Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces," pp. 456-457, Feb. 2022.
LINK
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[C3] ESSCIRC 2022: J. Ko, I. Jang, C. Kim, J. Park, C. Moon, S. Lee, and B. Kim, "A 50 Mb/s
Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body
Channel Moving at 0.75 Cycle/sec," pp. 213-216, 2022.
LINK
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[C4] ISOCC 2022: I. Jang, J. Seo, C. Moon, and B. Kim, "A Cost-efficient FPGA-based Embedded System
for Biosensor Platform," pp. 67-68, 2022.
LINK
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Next-Generation Optical Packaging Technology Development Project
National Research Foundation of Korea • July 2025–Present
Interposer Technology with Integrated Opto-Chiplets for CPO Based on 2.5D Optical Packaging
Strategic Industry-Academia Collaboration Project
Samsung Electronics Company Ltd. • September 2022–September 2025
16 Gbps Single-Ended Compact Transceiver
Published in IEEE Transactions on Circuits and System II: Express Briefs (TCAS-II) 2024 [J2].
Design and Application of Next-Generation Non-Volatile Memory Hierarchy
Samsung Electronics Company Ltd. Cluster Academia Collaboration Program • July 2021–June 2024
Inverter-Based Compact 4-Tap FFE Transmitter Development for Next-Generation Non-Volatile Memory
Presented in IEEE International Solid-State Circuits Conference (ISSCC) 2022 [C1] and published in IEEE Journal of Solid-State Circuits (JSSC) 2024 [J3]. Registered with U.S. patent [P1].
Patent
Innovation Protected by U.S. Patent
[P1] FEED FORWARD EQUALIZER AND SYSTEM INCLUDING THE SAME
LINK
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Patent No.: US12119963B2
Granted: October 2024
Novel addition-only FFE architecture that eliminates subtractive paths, reduces power consumption, and enhances robustness to quantization errors.
Honors and Awards
Recognition for Technical Excellence
[A2] Corporate Special Awards
Korea Semiconductor Design Contest • 2023
Awarded for Compact Single-ended Transceivers Demonstrating Flexible Generation of 1/N-rate Receiver Front-ends for Short-Reach Links [J4].
[A1] Corporate Special Awards
Korea Semiconductor Design Contest • 2022
Awarded for the development of addition-only FFE architecture that was later presented at ISSCC 2022 [C1].
Additional Experience
Teaching and Service
Alternative Military Service as Technical Research Personnel
POSTECH • March 2023 – February 2026 (expected)
Serving alternative military service while continuing research contributions in high-speed circuit design.
Teaching Assistant
POSTECH, Basic Circuit Experiments (EECE 281) • March 2019 – July 2019
Assisted undergraduate students with fundamental circuit experiments and laboratory instruction.
Reviewer Service
Peer Review Contributions
IEEE Journal of Solid-State Circuits (JSSC)
5 Reviews
Reviewed manuscripts on high-speed circuit design, analog/mixed-signal circuits, and wireline transceiver architectures.
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS I)
1 Review
Reviewed manuscripts on high-speed circuit design, analog/mixed-signal circuits, and wireline transceiver architectures.
2026 IEEE International Symposium on Circuits and Systems (ISCAS)
Reviewer
Serving as reviewer for conference submissions on circuits and systems design.
Technical Specialties
Deep Expertise in High-Speed Systems
Interconnect Modeling and Characterization
Electrical and optical modeling and characterization of various high-speed interconnects for chip-to-chip and optical links.
High-Speed I/O Circuit Design
Low-power, high-speed transmitters, receivers, FFE, DFE, CTLE, PLL, CDR, and clock distribution circuits for multi-Gbps operation.
On-Chip Measurement and Testing
Design of on-chip BERTs, PRBS generators, and eye monitoring circuits; implementation of FPGA and PC-based testing systems.
Skills
Silicon-Proven Toolchain & Languages
Programming
C/C++ and Python for modeling, firmware, and automation.
